Timing, noise, and power (TNP) analysis are crucial engines prior to signing-off a VLSI chip to manufacturing by performing a timing analysis to verify timing correctness, a noise analysis to determine the coupling effect of neighboring nets on a victim net in order and to verify that the glitch noise engine at the input of a sequential circuit, such as a flip-flop, does not impact its functionality. Added to these it should include a power analysis engine to compute the power consumption of the circuit to validate that power consumption of the chip to be less than a specified value set by the technology. Timing, noise, and power analysis are not independent of each other. For instance, power analysis results affect the timing results; the timing affects the noise, and the like. Accordingly, accurate timing, noise and power analysis is inevitable.
VLSI circuits consist of two major components, i.e., gates and corresponding interconnects. A nonlinear analysis is mainly used to achieve an accurate gate level analysis, while interconnects are generally modeled using linear elements, such as resistance, capacitance, and inductance. Several techniques exist to handle the linear interconnect analysis, the more relevant focusing on the gate level analysis.
To achieve accurate gate timing, noise, and power analyses, a gate timing, noise, and power libraries are required, typically characterized by Spice simulations that encompass the circuits under different conditions. Typical cell libraries include some of the most relevant cell attributes such as: delay/slew tables which are characterized and stored as function of input slew and output capacitive load; pin-cap; noise rejection curves, power related information, and the like. Recently, a more accurate current source modeling (CSM) has been advanced as an alternate modeling methodology. In addition to the traditional library data, a typical CSM based cell library includes additional attributes such as voltage/current waveform tables which are characterized and stored as function of input slew and output capacitive load; slew and output load dependent pin-caps; DC current tables characterized as a function of input voltage and output voltage and the like. Therefore, a more advanced CSM modeling paradigm requires significantly more memory resources compared to existing methodologies.
As process technologies scale down towards nanometer technology nodes, variability becomes a major concern in the design of VLSI circuits. Therefore, variability aware design automation tools (e.g. statistical static timing analysis tools) are required to accurately predict the behavior of the VLSI circuits. To perform process and environmental variation sensitive gate level analysis, and multiple libraries necessitate to be characterized at several processes, voltage, and temperature points. During a gate level analysis, the process, voltage, and temperature values of the each instance usage may differ from existing characterized libraries. Therefore, it becomes necessary to perform accurate and efficient gate level analysis, using the aforementioned characterized libraries.
Referring now to FIG. 1, a typical sample circuit is illustrated consisting of gates, 100, 101, 102, etc. and their respective interconnects, 103 and 104, and the like. To perform a timing analysis on the circuit, voltage signals 105 at the primary input pins 106 are propagated through the gates and interconnects until they reach the primary output pin 107 of the circuit. To perform a timing analysis, STA computes and propagates the timing quantities, such as voltage signal's arrival time, required arrival time, slew, and slack at every point of the timing graph.
Referring to FIG. 2, the circuit is illustrated having two instances of a same cell type at different voltage, temperature, and process variation setting. For instance, gate A 201 and gate B 202, are assumed to be the same cell type, e.g., a buffer. However, their respective voltage, temperature, input slew, and output load could be different. To perform an accurate timing analysis, it becomes necessary to determine how the timing behavior of the cells changes when the input slew, output load, process, voltage and temperature vary.
Referring to FIG. 3a, a typical timing library is shown consisting of a characterized input slew and an output load dependent non-linear delay, slew, voltage/current waveform tables for all the timing arcs of the cell. Also included are slew and load dependent pin-cap tables corresponding to the input pins of the gate. Given a value of input slew and output load during static timing analysis, a timer would extract an accurate delay, slew, and the like values from the tables.
Referring to FIG. 3b, a typical library, (also referenced to as LIB/ECSM library) is shown that includes characterized tables for power and noise analysis along with timing related attributes like delay, slew, waveforms, pin-caps, and noise at a given PVT point.
Historically, there have been two distinct methods for Complementary Metal-Oxide Semiconductor (CMOS) gate library characterization to parameterize Process, Voltage and Temperature (PVT) using a first approach that includes lookup tables for delay and slew. Typically, these include discrete process points, and scale factor sensitivities that are provided for variations. The second approach includes using empiric functions that cover more thoroughly the process space, but which require longer characterization time for each process node.
In today's world however, the impact of variations at smaller nodes results in an operating environment too diverse to be covered during characterization. More advanced methods, such as CSM, will allow for predictive techniques to model the gate behavior in diverse operating environments.
The difficulty associated with multiple libraries characterized at different process points resides in requiring the interpolation between them to compute delays, slews, waveforms, and the like. When the operating points require a large number of characterized libraries, a brute force interpolation approach at each instance becomes increasingly inefficient and inaccurate. In the case of CSM models, the inefficiency of interpolation is greater due to its inherent larger model size.
Conventional interpolation and/or extrapolation techniques used to determine the gate timing behavior at a point with predetermined values of process, voltage and temperature (referred hereinafter as PVT point) are mainly categorized in two groups:
Curve fitting that is generated by way of an equation that covers each library attribute for the entire PVT space. This technique has several shortcomings: firstly, some of the library attributes such as slew tables and waveforms tables include related information, therefore, using an independent curve fitting for slew tables and waveform tables can incur in certain inconsistencies in the resulting library at a PVT point. Secondly, the aforementioned technique becomes impractical in the presence of more complex attributes such as voltage and current waveforms as presented in ECSM (Effective Current Source Model) and CCS (Composite Current Source) libraries.
Performing timing, power, and noise analyses at each corner, and later interpolating and/or extrapolating the results achieved during timing/noise/power calculations are CPU intensive when the same operations are performed millions of times during an active run.